Non-volatile memory, or more precisely: flash memory, has become increasingly important for mass storage media, cards and code-products. Memory cells of a flash memory array are based on trapping of charge carriers in a floating gate or in a dielectric memory layer confined by thin confinement layers, e.g., an ONO-layer (Oxide-Nitride-Oxide) sequence. These non-volatile memory cells are electrically programmable and erasable.
Two major flash memory device concepts relate to so-called NOR- or NAND-flash devices. NOR-flash devices are suited for the storage of software and program files due to the considerably faster access to memory cells allowed by this flash concept. NAND-flash devices are suited for the storage of large amounts of user data due to its considerably smaller memory cell size.
Recently, an intermediate cell concept has been developed allowing the storage of two bits per cell. Therein, a wordline crossing an active substrate and provided with an ONO-layer sequence is designed to charge-trap channel hot electrons (CHE) in confined regions of the ONO-layer sequence on both sides of a channel or depletion region in the substrate. In other words, the charge carriers are trapped in a location of the ONO-layer sequence sandwiched between the wordline (or gate electrode) and the active substrate, where separated source and drain regions, the channel region and the gate electrode approach each other.
Charge carriers moving from source to a drain through the channel or depletion region are accelerated and gain enough energy in order to penetrate through the lower confinement layer of the ONO-layer sequence. These charge carriers are then trapped within the memory layer. As a result, the trapped charge carriers influence the threshold voltage of the cell transistor structure. Different programming states can then be read by applying the appropriate reading voltages.
As a consequence, programming and reading occurs by means of applying different voltages to each two bitlines connecting opposite source and drain regions of a transistor. Which of the two locations per cell is read out depends on the current direction according to the voltage drop between the two bitlines.
Although being based on the NOR-flash device concept, the memory array as described above, which is referred to as a “NROM”, has a considerably increased memory density because each cell can store two bits. As a result, the NROM-device concept may achieve advantages, which are typical of a NAND-flash device, while allowing fast memory cell access. For this purpose, the packaging of bitlines is increased in order to contact the source and drain regions. Each bitline is thus connected with each two source/drain regions per contact. The reason is that each memory cell has to be contacted by two different bitlines for providing the current measurement circuit for a respective memory cell.
FIG. 1 illustrates this concept in a top view of a portion of a memory array 10. Multiple wordlines WL cross over the substrate surface forming, among others, a transistor 31, which further comprises a source region 41 and a drain region 42. The bit storage locations are represented in this top view by the dots on the wordline boundaries. Multiple bitlines BL orthogonally traverse the wordlines WL within a superior metal level. Of those bitlines, bitlines BLI and BLI+1 are conductively connected to the source region 41, and the drain region 42 respectively. This connection is established by means of a stacked contact. The stacked contact comprises a local interconnect 21, 22 in a bottom portion and a bitline contact 51, 52 in an upper portion.
The local interconnects 21 or 22, respectively, connect each two source/drain regions 41, 43 and 42, 44 of each two neighboring memory cells along the wordline direction. The local interconnects 21, 22 are further provided with a contact 51, 52 for connecting the source/drain regions with the bitlines BLI or BLI+1, respectively. Contacts 51, 52, therefore, have an offset position with respect to transistor 31.
The result of this concept is that the density of bitlines may correspond with that density of the active areas yielding the respective source and drain regions 41, 42 of transistor 31. Note that the active areas are separated by regions provided with a shallow trench isolation (STI). Two of those STI regions are indicated as dotted areas in FIG. 1.
However, what is also visible from FIG. 1 is that the contacts 51, 52 must be manufactured with a considerably smaller width than the underlying local interconnects 21, 22 and that a high degree of alignment of the contacts 51, 52 with the bitlines BL is necessary.
According to a conventional process for manufacturing a memory array 10 such as that shown in FIG. 1, a contact is manufactured by depositing a dielectric layer upon a planarized surface that is formed above the wordlines WL and the local interconnects, which are already established. In the planarized surface, top sections of the local interconnects 21, 22 are exposed, i.e., laid open. A first lithographic step is applied to etch trenches for contacts 51, 52 into the dielectric layer down to the previously exposed local interconnects 21, 22. This is followed by a second lithographic structuring to etch the bitline trenches down to a predefined depth into the dielectric layer.
FIGS. 2a and 2b show side views of the resulting structures according to prior art. Note, that the same reference numerals denote the same features in the figures if not stated otherwise throughout this document. FIG. 2a shows a side view along line A-A of FIG. 1 and FIG. 2b shows a side view along a corresponding line B-B. Line B-B is parallel to the wordline direction, but actually extends between each two wordlines WLI, WLI−1.
An isolation layer 60 serves to separate each two local interconnects 21, 22 and a dielectric layer 61′ serves to separate bitlines BL from wordlines WL and from local interconnects 21, 22. Dielectric layer 61′ thus includes a function of an interlayer dielectric. Bitlines BL and contacts 51 are filled with conductive material by a damascene process. As can be seen from FIGS. 2a and 2b, alignment between the bitlines BL and contacts 51 is critical. A small amount of misalignment of the bitlines towards the left direction with respect to the contacts 51 is indicated by arrows in FIG. 2b. This misalignment may lead to shorts or at least to a smaller budget of overlay accuracy for the corresponding two lithographic mask processes.